As memory paging schemes have developed, certain formats have been frequently used. For example, one common paging scheme is to have up to 4 Gigabytes of memory divided into multiple 4-kilobyte pages. Directory entries and page table entries in such a scheme are 4-byte (32-bit) entries having a base address and multiple control bits that indicate permissions. For 16- and 32-bit processors, such a scheme is sufficient.
For many years operating systems have been written for paging schemes with 4-byte table entries and 4-kilobyte pages. However, processors that can address more than 4 Gigabytes of memory have been developed, and for these processors, providing more than 4 Gigabytes of memory with 4-kilobyte pages requires table entries of more than 4 bytes. Table entries of more than 4 bytes are used for memories larger than 4 Gigabytes because the formats used for 4 Gigabyte and smaller memories do not have enough bits available to support the larger addresses of memories larger than 4 Gigabytes in size.
Because many operating systems have been designed based on 4-kilobyte pages and 4-byte table entries, these existing operating systems cannot take advantage of memory beyond 4 Gigabytes. Therefore, what is needed is a memory paging system having 4-byte table entries and 4-kilobyte pages that can access more than 4 Gigabytes of physical memory. The present invention provides a memory paging system that accesses more than 4 Gigabytes of memory while maintaining 4-kilobyte pages. Thus, modifications to existing operating systems to access memory beyond 4 Gigabytes are greatly reduced compared to a memory paging systems having table entries larger than 4 bytes.